Prof. Dr.-Ing. Juliana Panchenko , TU Dresden
Friday Get-together: “From Microinterconnects to Systems: Advanced Packaging Technologies for HPC and AI”
21.08.2026 (Friday)
, 14:00 - 15:00
- Dresden: Barkhausenbau Room BAR E64A
- Aachen: new Walter Schottky Haus Room B101/B102
- Halle/RUB: at your institutions
- Online: https://tu-dresden.zoomx.de/j/87264138030?pwd=WG41dkN6L0NOaXFaaVRORzM3QmdFQT09
Abstract:
This presentation provides an overview of recent advances in fine-pitch interconnect technologies that enable advanced packaging solutions for high-performance computing (HPC) and artificial intelligence (AI) systems. The presentation will cover recent developments and results in microbump and hybrid bonding technologies, highlighting their role in achieving higher interconnect density, improved performance, and enhanced system integration. In addition, a brief overview of the research activities of the Institute of Electronic Packaging Technology in Dresden will be presented.
Bio:
Juliana Panchenko studied microelectronics at the National Technical University of Ukraine in Kyiv and completed her master's thesis (microstructure investigations of lead-free solder materials) during a research stay at the Institute of Electronic Packaging (IAVT) at the TU Dresden in 2009. She subsequently worked at the IAVT as a research associate and doctoral student, receiving her doctorate in 2013. During this time, she was a fellow in the DFG Research Training Group "Nano- and Biotechnologies for the Packaging of Electronic Systems" and a member of the SAB junior research group "Highly Reliable 3D Microsystems." She also completed a six-month research stay at IMEC in Belgium. During this time, Ms. Panchenko specialized in the field of micro-interconnection techniques with intermetallic phases (SLID or TLP) for 3D integration, publishing internationally recognized results, particularly in the field of microstructure analysis (SEM, EDX, EBSD). Since July 2014, she has been a junior professor for "Nanomaterials for Electronics Packaging" at the IAVT and, concurrently, a group leader in the field of 3D system integration and wafer-level packaging for 300 mm wafers at Fraunhofer IZM-ASSID.